1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor device which supports various option modes of data bandwidth and a method of driving the same.
2. Description of the Related Art
As the integration degree of semiconductor devices, such as DDR SDRAM (Double Data Rate Synchronous DRAM) is increased with the development of process technology, tens of millions of memory cells are provided in a single semiconductor device.
Such semiconductor devices are designed to operate according to data bandwidth options. Data bandwidth options are set to output a set bandwidth of data, and are defined specifications. For example, in a semiconductor device with eight data input/output pads, data input/output operations are performed through all eight data input/output pads when the data bandwidth option is set to X8 mode, or it is performed through only four of the data input/output pads when the data bandwidth option is set to X4 mode.
FIG. 1 is a diagram for explaining an operation of a conventional semiconductor device. FIG. 1 illustrates an operation based on the X4 mode.
Referring to FIG. 1, an active operation ACT1 is first performed. When the active operation ACT1 is performed, a predetermined word line is enabled to load first to eighth write data stored in first to eighth memory cells (hereafter, referred to as “first to eighth pre-write data”) into first to eighth bit lines, while charge sharing occurs between the first to eight memory cells and the first to eighth bit lines. Then, an amplification block amplifies the first to eighth pre-write data loaded in the first to eighth bit lines. For example, the amplification block amplifies a voltage difference between first pre-write data loaded in a first bit line BL0 and first inverted pre-write data loaded in a first bit line bar BLB0.
In such a state, a first write operation WT1 is performed.
A write driving block transmits first to fourth write data inputted through first to fourth input/output pads DQ0 to DQ3 to first to fourth local lines based on the X4 mode. For example, the write driving block may include first and second write driving units, and the first write driving unit transmits the first to fourth write data to the first to fourth local lines, while the second write driving unit is disabled.
A second common coupling block transmits the first to fourth write data loaded in the first to fourth local lines to first to fourth segment lines SIO0 to SIO3 according to a switching control signal IOSW. For reference, the second common coupling block may include ninth to 16th switching units, which are turned on according to the switching control signal IOSW, and the first to fourth write data are transmitted through the ninth to 12th switching units among the ninth to 16th switching units.
A first common coupling block transmits the first to fourth write data loaded in the first to fourth segment lines SIO0 to SIO3 to the first to fourth bit lines according to a column select signal YI. For reference, the first common coupling block may include first to eighth switching units, which are turned on according to the column select signal YI, and the first to fourth write data are transmitted through the first to fourth switching units among the first to eighth switching units.
At this time, the first to fourth pre-write data loaded in the first to fourth bit lines are changed to the first to fourth write data, and the fifth to eighth pre-write data loaded in the fifth to eighth bit lines are retained as they are.
A memory block stores the first to fourth write data loaded in the first to fourth bit lines, and stores the fifth to eighth pre-write data loaded in the fifth to eighth bit lines.
Then, a second write operation WT2 is performed.
The write driving block transmits the fifth to eighth write data inputted through fifth to eighth input/output pads (not illustrated) to fifth to eighth local lines based on the X4 mode, For example, the second write driving unit transmits the fifth to eighth write data to the fifth to eighth local lines. The first write driving unit is disabled.
The second common coupling block transmits the fifth to eighth write data loaded in the fifth to eighth local lines to fifth to eighth segment lines according to the switching control signal IOSW. For reference, all of the ninth to 16th switching units SW10 to SW17 are turned on according to the switching control signal IOSW, and the fifth to eighth write data are transmitted through the 13th to 16th switching units among the ninth to 16th switching units,
The first common coupling block transmits the fifth to eighth write data loaded in the fifth to eighth segment lines to the fifth to eighth bit lines according to the column select signal YI. For reference, all of the first to eighth switching units are turned on according to the column select signal YI, and the fifth to eighth write data are transmitted through the fifth to eighth switching units among the first to eighth switching units.
At this time, the fifth to eighth pre-write data that is loaded in the fifth to eighth bit lines are changed into the fifth to eighth write data, and the first to fourth write data that is loaded in the first to fourth bit lines are retained as they are.
The memory block stores the first to fourth write data that is loaded in the first to fourth bit lines, and stores the fifth to eighth write data that is loaded in the fifth to eighth bit lines.
As described above, when the fifth to eighth pre-write data that is loaded in the fifth to eighth bit lines are changed to the fifth to eighth write data, the first to fourth write data that is loaded in the first to fourth bit lines are to be retained as they are.
Referring to FIG. 1, however, while the second write operation WT2 is performed, the first to fourth write data are not retained as they are, but changed to other data. This is because, when the fifth to eighth switching units and the 13th to 16th switching units for transmitting the fifth to eighth write data are turned on, the first to fourth switching units and the ninth to 12th switching units are turned on together. In other words, since the first to fourth local lines and the first to fourth segment lines are electrically coupled to the first to fourth bit lines, in a state where the first write driving unit is disabled, charge sharing occurs between the first to fourth write data, loaded in the first to fourth bit lines, and electric charges remaining in the first to fourth segment lines and the first to fourth local lines. The first to fourth write data are unexpectedly changed. For reference, since the first to fourth local lines are longer than the first to fourth segment lines, parasitic capacitance of the first to fourth local lines is greater than the parasitic capacitance of the first to fourth segment lines. Due to the parasitic capacitances of the first to fourth segment lines and the parasitic capacitances of the first to fourth local lines, the charge sharing value may be increased.
When the first to fourth write data are unexpectedly changed, as described above, the next read operation RD1 may fail. This failure is referred to as X4 flipping error.